1. Field of the Invention
The present invention relates to a bit length converting circuit, for floating-point numbers, suitable for reducing the amount of calculation and circuit scale, and a vibration correction control circuit using the bit length converting circuit.
2. Description of the Related Art
Digital still cameras and digital movie cameras (hereinafter generically referred to as digital cameras) have been widely used by general users. Users who are not familiar with how to handle the cameras properly are likely to encounter camera shake when taking pictures. Note here that the term “camera shake” will be hereinafter referred to simply as “shake”. Also, the digital camera is generally assembled into a mobile device such as a mobile phone, a smart phone, and a PDA (Personal Digital Assistant). Most of the cameras incorporated into such mobile devices are so designed that the camera is held by one hand only while taking pictures or video. Where the camera is held by one hand, the shake is more likely to occur as compared with when the camera is held by both hands to take pictures or video.
An optical shake correction method is available to correct the shake. In this optical shake correction method, an optical axis is corrected by a vibration detecting element for detecting the vibration of a camera and a driver element that moves a lens position in such a direction as to cancel out the displacement caused by the vibration. Generally used is a mechanism where a lens is mounted within a correction frame using a spring and the position of the lens is moved by an X-axis actuator and a Y-axis actuator in such a direction as to cancel out the displacement caused by the vibration.
For an optical shake correction using the above-described mechanism, it is conceivable that the output values of the vibration detecting element (e.g., gyro sensor) are represented by floating-point numbers. The floating-point numbers are widely used as a method for representing decimal numbers. The IEEE 754 format is a representative method for representing floating-point numbers. The IEEE 754 format has a single precision representation and a double precision representation. In the single precision representation represented by a total of 32 bits, a sign part is represented by 1 bit, an exponent part by 8 bits, and a fraction part (mantissa) by 23 bits.
However, the floating-point number of 32 bits is more than necessary for the above-described shake correction. For that purpose, the 32 bits require too large a circuit size, which results in a loss of efficiency. Thus, arithmetical operations may be done using a bit length of the floating-point number long enough to meet the actual needs. However, a problem with such a proposition is the inflexibility of general CPUs and external digital circuits in handling the interfaces other than 32 bits and 64 bits. In other words, the existing computational resources cannot be put to ready use.